(1) Field
This relates generally to NMOS switches and relates more specifically to a method and system for limiting the slew rate of the output voltage of one or more high side (HS) NMOS power switches.
(2) Description of the Related Art
High-side NMOS switches are seen to be preferable to PMOS switches in several respects. Typically, NMOS switches have an RDSon, i.e. a drain to source resistance in on-state, which is about a factor of two times lower than the drain to source resistance of PMOS switches. Furthermore, the parasitic body diodes of NMOS switches are both pointing to the substrate or to a freely available bulk node in case of an isolated device, which tends to ease system design.
On the other hand, the use of NMOS transistors as a high-side switch also has drawbacks. When using enhancement type NMOS transistors that are available on standard CMOS processes, the gate terminal of the transistor has to be biased positive with respect to its source terminal, in order to drive the transistor in strong inversion. Consequently, if the transistor is connected as a high-side switch, the gate node typically must be driven above the positive voltage rail, i.e. the gate node typically must have a higher potential than the source terminal that is connected to the positive voltage rail. Therefore, it is usually required to provide a charge pump in order to supply the gate bias. In view of the costs and design constraints involved when using charge pumps, it is desirable to limit the number of required charge pumps. In particular, it is desirable to reduce the number of charge pumps, which are required for an array, or a plurality of NMOS switches. In order to avoid the requirement of charge pumps altogether, it is current practice to use PMOS switches, even though they exhibit the above-mentioned shortcomings.
A further aspect to consider is the control of the inrush current of a switch, which is being switched to on-state. Current practice for inrush current control using PMOS switches is e.g. a two-phase approach using two switches connected in parallel. In an initial phase, a first switch having a relatively high RDSon is closed or activated. Its relatively high resistive drop ensures a relatively slow rise time of the current and therefore limits the inrush current. After a certain time the main switch, i.e. a second switch being parallel to the first switch and having a relatively low RDSon, is closed or activated. This two-phase approach has the effect that during the first phase of the turn-on, the overall switch comprising the two parallel switches has a high RDSon. High resistive load conditions on the output of the overall switch could therefore lead to a situation, where the output voltage does not rise until the second phase of the turn-on, i.e. until the resistive RDSon value of the overall switch is reduced. In such a case the turn-on upon closing of the second switch will be relatively steep during the second phase, causing a high inrush current, despite the two-phase approach.
In view of the multiple advantages of enhancement type NMOS switches, it is a challenge for engineers to design methods and circuit arrangements for controlling the slew rate of one or more enhancement type NMOS switches while reducing the number of required charge pumps. In other words, to design a driver for a NMOS switch or an array of NMOS switches that controls the slew rate and which requires a reduced number of charge pumps. Furthermore, it may be beneficial to reduce the current, which is drawn from the charge pump(s) during steady state operation of the one or more NMOS switches.